Circuit arrangement for voltage regulation

ABSTRACT

A circuit arrangement for voltage regulation comprises an output, a controllable output transistor connected to the output, an error detection circuit, and a monitoring control circuit. A voltage-regulated output potential can be tapped off the output, the controllable output transistor is connected to the output on a load side and the output transistor comprises a control terminal. The error detection circuit provides a regulating signal if a deviation between the output potential or a potential derived from the output potential and a desired value occurs. By means of the regulating signal the control terminal can be charged or discharged dependent on the deviation and the monitoring control circuit monitors the regulating signal and performs, if the regulating signal lies outside a predetermined range, an additional charging or discharging of the control terminal until the regulating signal lies within the predetermined range.

BACKGROUND OF THE INVENTION

The invention relates to a circuit arrangement for voltage regulation.

For the operation of electrical and microelectronic circuits, DCvoltages are required which have a voltage value that is complied withover the entire range of the power supply voltage fluctuations, loadcurrent fluctuations and temperature fluctuations that occur. For thesereasons, a supply voltage is typically not directly suitable asoperating voltage, but rather has to be stabilized and smoothed by meansof a voltage regulator connected downstream that is providedspecifically for this purpose.

Voltage regulators are available—according to the variousapplications—in a multiplicity of different embodiments and variants.With increasing integration of microelectronic circuits and also withthe trend toward operating these microelectronic circuits with an everlower voltage supply, there is increasingly a demand for voltageregulators having a very low voltage drop. Such voltage regulators arereferred to in the relevant literature as so-called “low-drop” voltageregulators. Low-drop voltage regulators work correctly even when thevoltage drop between the supply voltage and the regulated output voltageis less than 1 V and, in particular, corresponds to a fraction of avolt. The present invention and also the problem area on which it isbased are described below with regard to low-drop voltage regulators,although without restricting the invention thereto.

An essential task of such low-drop voltage regulators is to provide astabilized supply voltage for an electronic circuit or a correspondingload. In this connection it is desirable for the low-drop voltageregulator to have the best possible regulation characteristic, so thatthe stabilized output voltage that is regulated by said regulator andprovided at the output is therefore as constant as possible.Furthermore, the low-drop voltage regulator should be able stillreliably to regulate extremely low voltage drops. A further requirementis for the low-drop voltage regulator to provide a largest possiblevoltage range for the input voltage on the input side and for it to beable, in particular, to regulate both high and low input voltages. It isfurthermore essential for the low-drop voltage regulator to have aminimum power consumption during operation and, moreover, a minimumpower loss.

FIG. 1 of the drawing shows a circuit arrangement of a conventionallow-drop voltage regulator, which in this case has a PMOS transistor 1as output transistor. The PMOS 1 is arranged with its controlled pathbetween a supply terminal 2 having a supply potential VDD and an output3, at which a regulated output potential VOUT is present. The outputpotential VOUT is fed via a feedback path 8 to an amplifier 4, whichcompares the output potential VOUT with a reference potential VREF andgenerates, depending on this comparison, on the output side, a controlpotential for driving the PMOS transistor 1. What is problematic withthis type of voltage regulation is the low stability of the regulatingloop and a comparatively long response time, which can essentially beattributed to the use of the PMOS transistor 1.

It would be desirable, therefore, to use an NMOS transistor as outputtransistor since this component already has a very good regulationcharacteristic on account of its intrinsic properties. FIG. 2 shows alow-drop voltage regulator which has an NMOS transistor 5 connected insource follower connection as output transistor, that is to say whichacts to a first approximation as a constant voltage source. In thiscase, the control terminal of the NMOS transistor 5 must be able to becharged to a voltage that is higher than the supply potential VDD. Thiscan be realized in a simple manner by means of a charge pump 6, whichcharges the control terminal of the NMOS transistor 5. A dischargingtransistor 7 is furthermore provided, which, as necessary, dischargesthe control terminal of the NMOS transistor 5 again and thus switchesoff the NMOS transistor 5. The discharging transistor 7 can be driven bymeans of a signal derived from the output potential VOUT or a suitablychosen control signal. Such a low-drop voltage regulator is described ina similar form for example in U.S. Pat. No. 5,675,241.

What is problematic about this type of a low-drop voltage regulator isthe power consumption thereof. The energy efficiency of such a circuitarrangement is relatively poor, since, with this type of voltageregulation, the charge pump 6 supplies the NMOS transistor 7 with apermanent charging current, which is then reduced again by thedischarging transistor 7. If the NMOS transistor 7 is not supplied witha permanent charging current, then although a more favorable energyefficiency results, this is at the expense of a significantly poorerregulation characteristic.

FIG. 3 shows a further low-drop voltage regulator such as is described,for example, in European patent No. 0 846 996 B1. The voltage regulatorin this case has two regulating stages 10, 11. An essential constituentpart of the first regulating stage 10 is a charge pump 6, which suppliesthe NMOS transistor 5 with a charging current on the output side. Theregulation of this first regulating stage 10 is relatively slow,although it enables a high gain on account of the relatively highcharging current. Relatively fast disturbances are corrected by means ofthe second regulating stage 11, which although it provides a very fastregulation, nonetheless has a relatively low gain. A constituent part ofthe second regulating stage 11 is an inverting amplifier 12, whichcontinuously compares the output potential VOUT, which is divided downby means of a voltage divider 13, with a reference signal VREF andprovides a regulating potential VR on the output side depending on thecomparison. By means of a capacitor 14, the potential is then matched tothe control terminal of the NMOS transistor. At the same time, saidregulating potential VR is fed to the charge pump 6 as control signalvia an operational amplifier 15.

What is problematic about this solution, however, is that two regulatingstages 10, 11 are required for regulating the output potential VOUT,which regulating stages are coupled to one another and thus virtuallymutually impede one another in their action. By way of example, eitherthe first regulating loop 10 is dominant, as a result of which thefunctioning thereof is then impeded by the second regulating loop 11,however. Alternatively, fast voltage changes are intended to becorrected, with the result that the second regulating loop 11 is thendominant. However, said second regulating loop 11 is then impeded in itsaction by the first regulating loop 10, and vice versa.

For the stability of the entire voltage regulation it is necessary,therefore, to provide a greater or lesser circuit outlay in order thatboth the slow regulation with high gain and at the same time the fastregulation with low gain are coordinated with one another. This isextremely difficult in many applications, particularly if a highlydynamic, i.e. very fast, correction of very low voltage drops isinvolved. In reality, this typically leads to a relatively complexcircuit arrangement of the voltage regulator, in particular as far asthe coordination of the two regulating circuits 11, 12 with one anotheris concerned. As a result of this additional circuitry outlay, however,this type of a low-drop voltage regulator becomes more or lesscost-intensive, which in many applications does not justify theadvantage obtained by the two-stage regulation.

In a manner similar to that in the case of the circuit arrangement inFIG. 2, in the case of the circuit arrangement in FIG. 3 as well, thecontrol terminal of the NMOS transistor 5 is charged permanently sincethe charge pump 6 supplies said control terminal with a permanentcharging current. This is not very energy efficient—in a similar mannerto that in the case of the exemplary embodiment in FIG. 2.

To compound matters, the charge pump 6 is a regulated charge pump whichtherefore provides a variable output voltage in a manner dependent onits input voltage. The provision of a regulated charge pump isrelatively costly and complex in terms of circuitry and is notespecially efficient for energetic reasons.

BRIEF DESCRIPTION OF THE INVENTION

In one aspect of the invention, a circuit arrangement for voltageregulation comprises an output, at which a voltage-regulated outputpotential can be tapped off, a controllable output transistor connectedto the output on the load side, an error detection circuit, whichprovides a regulating signal in the event of a deviation of the outputpotential or a potential derived therefrom from a desired value, bymeans of which regulating signal a control terminal of the outputtransistor can be charged or discharged in a manner corresponding to thedeviation, and a monitoring control circuit, which monitors theregulating signal and which, in the case where the regulating signallies outside a predetermined voltage range, performs an additionalcharging or discharging of the control terminal until the regulatingsignal lies within the predetermined range again.

The idea on which the present invention is based consists, in the caseof a low-drop voltage regulator, in dispensing with a two-stage voltageregulation in order to provide the two functionalities of both fastregulation and equally efficient regulation, that is to say regulationfurnished with a sufficiently high gain. Rather, the present inventionenvisages that during operation of the voltage regulator, generally onlya single, so-called fine regulation of the voltage is necessary in orderto correspondingly activate the control terminal of the outputtransistor and thereby perform the regulation. In this case, the fineregulation is carried out by an error detection circuit specificallyprovided for this purpose. The regulation is effected on the basis ofthe regulated output potential—or a potential derived therefrom by meansof a voltage divider for example—in comparison with a desired value. Thedesired value used may be, by way of example, a suitable referencepotential preferably lying within a predetermined voltage range, or acontrol potential provided by a bandgap monitoring circuit. Said voltagerange is designed such that within said predetermined voltage rangeexclusively the fine regulation is active and undertakes the regulation.

For the case where in contrast a more powerful regulation is requiredsince, by way of example, very high overvoltages or undervoltages arepresent, it is necessary additionally or alternatively to implement afurther possibility of setting the control potential of the outputtransistor. In this case of an excessively high or excessively lowvoltage at the output of the error detection circuit, an operating pointadjusting device, the method of operation of which is virtuallycomparable but not identical to a coarse regulation, is connected in,for example by a charge pump or a discharging circuit beingsupplementarily connected as constituent part of the operating pointadjusting device depending on the presence on an undervoltage orovervoltage. This charges or discharges the control terminal of theoutput transistor until the regulating potential provided by the errordetection circuit lies within a predetermined voltage range again. Theoperating point adjusting device is subsequently deactivated again, sothat exclusively the fine regulation by means of the error detectioncircuit is then active.

Since this case of an excessively high or excessively low voltage occursrelatively infrequently during operation of a voltage regulator, on theone hand the charge pump can remain deactivated for long stretches,which is particularly advantageous for reasons of an improved energyefficiency. On the other hand, it is advantageously possible to userelatively simple pull-up transistors having small dimensions for thecharge pump, which consequently provide a relatively low chargingcurrent in comparison with previous voltage regulators and conventionalcharge pumps. This is also sufficient since the case of charging thecontrol potential of the output transistor has to be performedrelatively infrequently and usually not to the full amount, which isparticularly advantageous in energetic terms. Furthermore, the chargepump as well as the discharging circuit can be realized by very simplecircuitry elements and, moreover, given relatively small dimensions.

A further advantage of the inventive voltage regulator is that herethere are not two regulating loops which operate antagonistically andthe regulations of which operate virtually antagonistically andconsequently have to be coordinated with one another in complex fashion,as is the case in some of the known voltage regulators mentioned in theintroduction. In the case of the present invention, only a singleregulation, namely the fine regulation, is active during normaloperation. It is only in a few cases that the operating point adjustingdevice is additionally or alternatively activated by supplementarilyconnecting the charge pump or the discharging circuit, which, however,is active only for a short time. This is subsequently deactivated again.A complex coordination of this operating point adjusting device is notnecessary. The voltage regulator according to the invention is thereforealso distinguished by a very simple topography in terms of circuitry.

What is essential to the invention here is that the charge pump forcharging the control terminal of the output transistor only has to beswitched on momentarily, only when the charge provided by the levelconverter is insufficient. In this case, the magnitude of the chargingcurrent made available is not significant. This constitutes asignificant improvement of a known voltage regulator, as illustrated inEP 846 996 B1 mentioned in the introduction, in which the charge pump ispart of a continuously embodied two-stage regulation.

The particular advantage in the case of the inventive voltage regulatoralso consists in the fact that the error detection circuit and hence theregulating stage of the voltage regulator is able to carry out a voltageregulation even in the event of great deviations (ripple) of the supplyvoltage, which is otherwise regulated only by means of a sufficientlystrong charge pump.

By means of the error detection circuit and also the monitoring controlcircuit, a regulation mechanism which enables a time-continuousregulation without any interruption to the regulation can be realized ina very simple yet nonetheless highly effective manner.

The output transistor may be formed as an n-channel MOSFET or NMOStransistor for short. Particularly in the case of use in a powerelectronic circuit, it is advantageous, moreover, to use a power MOSFETas the output transistor.

The output transistor may typically be formed in a source followerconnection, in which case, therefore, its drain terminal is connected toa first supply terminal, at which the first supply potential is present,and its source terminal is connected to the output.

One embodiment of the inventive voltage regulator, in terms ofcircuitry, is very simple and efficient, the error detection circuit isformed as an inverting amplifier in the case of an NMOS outputtransistor. The output potential or a potential derived therefrom is fedto the amplifier, which may be an operation amplifier for example, onthe input side, said amplifier comparing said potential with the desiredvalue or a reference potential. Depending on this comparison, theamplifier provides, on the output side, a correspondingly amplifiedregulating signal, preferably a regulating potential, which can be usedfor setting the control potential of the output transistor.

In a further embodiment, a level converter is provided, which ispreferably connected downstream of the error detection circuit. Thelevel converter converts the level of the regulating signal or of theregulating potential of the error detection circuit into the controlpotential, so that the control potential thus obtained is shifted by aspecific voltage magnitude with respect to the control potential. In arefinement which, in terms of circuitry, is particularly simple andtherefore preferred, the level converter is formed as a capacitiveelement, in particular as a capacitor.

Another embodiment of the inventive voltage regulator provides acontrollable charging and/or discharging circuit as constituent part ofan operating point adjusting device, which is/are designed to charge thecontrol terminal of the output transistor with a charging current and/orto discharge it with a discharging current. A controllable chargingcircuit is preferably formed as a charge pump for providing the chargingcurrent. Such a charge pump may be equipped e.g. with simple pull-uptransistors. The controllable discharging circuit may likewisepreferably have a discharging current source and, in particular, acontrollable MOSFET for providing the discharging current.

At least the controllable charging circuit and/or the dischargingcircuits may be coupled to the monitoring control circuit on the controlside. In this case, the monitoring control circuit provides at least onecontrol signal, by means of which the charging and/or dischargingcircuit can be activated and/or also deactivated again as necessary.

In an alternative embodiment of the inventive voltage regulator, theerror detection circuit comprises a bandgap monitoring circuit, which isarranged on the supply side between the output and a second supplyterminal and which monitors a bandgap voltage dependent on the outputpotential. The bandgap monitoring circuit provides the regulating signalon the output side if no bandgap voltage is present. If the bandgapvoltage is present, the bandgap monitoring circuit does not generate aregulating signal, with the result that in this case no fine regulationis carried out either. In this case, the control signal is sufficientfor the activation of the output transistor and does not have to bereadjusted.

In another embodiment of the inventive voltage regulator, a voltagedivider, preferably a resistive voltage divider, is provided between theoutput of the output transistor and an input of the error detectioncircuit, which voltage divider divides down the output potential in amanner corresponding to its division ratio. In this way, as required theregulated output potential fed to the error detection circuit on theinput side can be set in a targeted manner to a value coordinated withthe reference potential.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The present invention is explained in more detail below on the basis ofthe exemplary embodiments specified in the schematic figures of thedrawing, in which:

FIG. 1, as discussed above, is a circuit arrangement of a first low-dropswitching regulator for elucidating the general problem area.

FIG. 2, as discussed above, is a circuit arrangement of a secondlow-drop voltage regulator for elucidating the general problem area.

FIG. 3, as discussed above, is a circuit arrangement of a third low-dropvoltage regulator disclosed by European patent No. 0 846 996 B1.

FIG. 4 is a general block diagram of a low-drop voltage regulatoraccording to the invention.

FIG. 5 is a detailed block diagram of a first exemplary embodiment of aninventive low-drop voltage regulator.

FIG. 6 is a schematic diagram for illustrating the thresholds of themonitoring control circuit.

FIG. 7 is a detailed block diagram of a second exemplary embodiment ofan inventive low-drop voltage regulator according to the invention;

FIG. 8 is a block diagram of a third exemplary embodiment of aninventive low-drop voltage regulator according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

In the figures of the drawings, identical and functionally identicalelements, features and signals—unless explained otherwise—are providedwith the same reference symbols.

FIG. 4 shows a general block diagram of a low-drop voltage regulatoraccording to the invention, which is designated as voltage regulator 20hereinafter only for short. The voltage regulator is designated byreference symbol 20 in FIG. 4. The voltage regulator 20 has an outputtransistor 21, which may be formed as a power transistor for example.According to the invention, said output transistor is formed as an NMOStransistor 21 and forms the regulating transistor for regulating anoutput potential VOUT. The NMOS transistor 21 is arranged with itscontrolled path between a first supply terminal 22 and an outputterminal 23. A first supply potential, for example a positive supplypotential VDD, is present at the first supply terminal 22, whereas avoltage-regulated output signal VOUT derived from the first supplypotential VDD can be tapped off at the output terminal 23. The NMOStransistor 21 is thus connected in source follower connection.

The voltage regulator 20 furthermore has a charge pump 24, which isdesigned to generate, on the output side, a charging current IL forcharging a control terminal G to a control potential VG of the NMOStransistor 21. Furthermore, a discharging circuit 25 may be provided,which is likewise connected to the control terminal G and whichdischarges the control terminal G by means of a discharging current IEas necessary.

According to the invention, the voltage regulator 20 has an errordetection circuit 26. On the input side, the error detection circuit 26is connected to the output terminal 23 and also to a reference input 27,at which a reference potential VREF is present. An output node 28 of theerror detection circuit 26 is connected to the control terminal G of theNMOS transistor 21.

A level converter 29 is furthermore arranged between the output node 28and the control terminal G. The potential V1 present at the output node28 often lies significantly below the first supply potential VDD, sothat the potential V1 does not suffice for charging the control terminalG. In this case, the level converter 29 shifts the potential V1 in acorresponding manner. Said potential is thus suitable for switching onthe NMOS transistor 21.

According to the invention, a monitoring circuit 30 is provided inaddition to the error detection circuit 26. On the input side, themonitoring circuit 30 is connected to the output node 28 of the errordetection circuit 26. On the output side, the monitoring circuit 30drives the charge pump 24 with a control signal S1 and the dischargingcircuit with a control signal S2.

The functioning of the voltage regulator 20 according to the inventionis explained briefly below.

During operation of a voltage regulator 20, with charge pump 24activated, the control terminal G can be charged with a charging currentIL until the NMOS transistor 21 is correspondingly controlled into theon state. The charge pump 24 can subsequently be turned off. In theideal case, the potential VG at the control terminal G of the NMOStransistor 21 would then remain constant, whereby the NMOS transistor 21remains switched on. Without further regulation of the supply potentialVDD, an output potential VOUT present at the output terminal 23 wouldcorrespond to an unregulated supply potential VDD. In order, then, toprovide a voltage-regulated output potential VOUT, the voltage regulator20 according to the invention has the error detection circuit 26 and themonitoring circuit 30. The error detection circuit 26 compares theoutput potential VOUT with a reference potential VREF and generates anerror potential V1 on the output side depending on this comparison. Theerror potential V1, which is a measure of the difference between theoutput potential VOUT and the reference potential VREF, is convertedinto a control potential VG by a suitably dimensioned level converter29. Depending on said error potential V1 or the corresponding controlpotential VG, the NMOS transistor 21 is thus turned on to a greater orlesser extent, so that a very fast and highly effective regulation ofthe output potential VOUT is possible in this way.

The charge pump 24 thus serves the purpose of presetting the controlpotential VG at the gate terminal G of the NMOS transistor 21 and hencethe operating point thereof approximately to the desired controlpotential VG, in which case the control potential VG need notnecessarily be set exactly here. The fine regulation of the controlpotential VG is then effected by means of the error detection circuit 26and the level converter 29 connected downstream. A monitoring controlcircuit 30 is additionally provided, which monitors the regulatingpotential V1 with regard to overvoltage or undervoltage. The monitoringcontrol circuit 30 detects whether the regulating potential V1 liesabove or below a predetermined voltage threshold SATP, SATL (see FIG.6). If the regulating potential V1 lies within these thresholds SATP,SATL, then only the error detection circuit 26 undertakes the regulationfor setting the control potential VG of the NMOS transistor 21. If, bycontrast, the regulating potential V1 lies outside, that is to say aboveor below, the predetermined voltage thresholds SATP, SATL, then themonitoring circuit 30 correspondingly drives the charge pump 24 or thedischarging circuit 25 by means of the control signals S1, S2. In thiscase, the charge pump 24 or the discharging circuit 25 is usuallycontrolled into the switched-on state in order thereby to performcharging or discharging of the control terminal G to the controlpotential VG.

As soon as the regulating potential V1 lies within the thresholds SATL,SATP and thus within the active range 33 again, the discharging circuit25 or the charge point 24 is switched off again and thus deactivated—incontrast to EP 846 996 B1 described in the introduction. The charge pump24 and the discharging circuit 25 thus function as an operating pointadjusting circuit and not as regulating circuits, as is the case in EP846 996 B1. Consequently, the voltage regulator according to theinvention only has a single regulation, also designated as fineregulation above, and also a device 24, 25, 30 for operating pointadjustment or for operating point setting.

FIG. 5 shows a more detailed illustration of the voltage regulatoraccording to the invention by comparison with the general illustrationin FIG. 4. Here the error detection circuit 26 has an invertingamplifier 34. Here the level converter is formed as a capacitor 29 andthe discharging circuit 25 is formed as an NMOS transistor 31. Thecontrolled path of the NMOS transistor 31 is connected between thecontrol terminal G of the NMOS transistor 21 and a second supplyterminal 32, at which a second supply potential GND, for example thepotential of the reference ground GND, is present. On the control side,the NMOS transistor 31 is driven with the control signal S2 by means ofthe monitoring control circuit 30.

During operation, after an initial charging of the control terminal VG,the charge pump 24 and also the discharging circuit 25 are in theswitched-off state. This also results in a high energy efficiency of thevoltage regulator 20, since the control terminal G of the NMOStransistor 21 is not permanently charged with a charging current IL.During operation, the charge pump 24 merely serves the purpose ofcharging the control terminal G of the NMOS transistor 21 if the chargestored in the capacitor 35 is no longer sufficient in the course ofoperation for example on account of leakage currents.

Here the fine regulation is exclusively carried out by means of theerror detection circuit 26 and by means of the level converter 29connected downstream. A time-continuous regulation is provided in thisway.

The function of the monitoring control circuit 30 shall be describedbriefly below with reference to the schematic illustration in FIG. 6.Here the upper and the lower voltage thresholds are designated by SATPand SATL, respectively. The voltage range between the upper and lowerthresholds SATP, SATL designates the active voltage range 33 withinwhich the regulating potential V1 should lie. The monitoring controlcircuit 30 monitors whether the regulating potential V1 is within theactive voltage range 33 or gets close to the limits thereof. If theregulating potential V1 at the output terminal 28 exceeds the uppervoltage threshold SATP, then the monitoring control circuit 30 activatesthe charge pump 24 by means of the control signal S1. The charge pump 24is switched on and supplies the control terminal G with a chargingcurrent IL until the regulating potential V1 again lies below SATP andthus within the voltage range 33. The monitoring control circuit 30activates the discharging circuit 25 in the same way, so that thecontrol terminal G is discharged by means of the discharging current IEif and for as long as the regulating potential V1 lies below the voltagethreshold SATL.

In FIG. 6, reference symbol 36 designates an upper hysteresis range forthe upper voltage threshold SATP and 37 designates a lower hysteresisrange for the lower voltage threshold SATL. It is expedient to provide ahysteresis range 36, 37 in order to prevent the corresponding chargingor discharging circuit 24, 31 from being continuously switched on andoff momentarily when the regulating potential V1 is in the region of oneof the two thresholds SATP, SATL.

As will be described below with reference to FIG. 7, the lowerhysteresis range 37 can be realized by means of a discharging transistor31 controlled by means of a bias voltage VBIAS and arranged with itsload path in parallel with the level converter, said dischargingtransistor virtually performing a self-regulation. The upper hysteresisrange 36 can be realized by means of a corresponding device oralternatively also by means of a suitable control device (notillustrated in the figures).

FIG. 7 shows a second exemplary embodiment of a voltage regulator 20according to the invention. In contrast to the exemplary embodiment inFIG. 5, here the NMOS transistor 31 of the discharging circuit 25 isarranged with its controlled path in parallel with the capacitor 29 ofthe level converter. Here, therefore, the NMOS transistor 31 of thedischarging circuit 25 is not driven by means of the monitoring controlcircuit 30, but rather by means of the BIAS voltage VBIAS. Here the NMOStransistor 31 is preferably designed such that the lower voltagethreshold SAPL approximately corresponds to the bias voltage VBIAS minusthe threshold voltage Vth of the NMOS transistor 31. If the regulatingpotential V1 becomes too low in this case, then the NMOS transistor 31is automatically controlled into an on state, as a result of which thecontrol terminal G of the NMOS output transistor 21 is discharged. As aresult, the output potential VOUT becomes lower, as a result of whichthe error detection circuit 26 raises the potential V1 at the outputterminal 28 again, which directly leads to the NMOS transistor 31 beingswitched off again. A dynamic self-regulating regulation mechanism isprovided in this way, which discharges the control terminal G of theNMOS transistor 21 precisely to the extent required for the provision ofa voltage-stabilized, regulated regulating potential V1.

Preferably, but not necessarily, the charge pump 24 contains so-calledpull-up transistors designed in a relatively weak fashion. This meansthat the charge pump 24 and, consequently, its charge pump current ILcan be limited to a relatively low current value for reasons of energyefficiency. This is possible by virtue of the fact that the controlterminal G does not have to be supplied with a permanent chargingcurrent IL, but rather is charged only once and momentarily and theactual regulation is effected by means of the error detection circuit 26and also the level converter 29.

FIG. 8 shows a third exemplary embodiment of a voltage regulator 20according to the invention. In contrast to the exemplary embodiment inFIG. 5, here a bandgap monitoring circuit 38 is arranged between theoutput terminal 23 and the output terminal 28 instead of the errordetection circuit 26. A bandgap-based voltage VBG is thus intended to bedropped between the output terminal 23 and a second supply terminal 32,at which the reference-ground potential GND is present. The bandgapmonitoring circuit 38 is formed in such a way that it provides aregulating potential V1 at the output 28 in the event of deviation ofthe output voltage from a desired voltage, analogously to the functionof the amplifier 26 in FIG. 4. In particular, the bandgap monitoringcircuit 38 then provides a regulating potential V1 if no bandgap-basedvoltage VBG is present. If a bandgap-based voltage VBG is present, thenthe bandgap monitoring circuit 38 does not set a regulating potential V1at the output 28, with the result that no fine regulation of the controlpotential VG is effected in this case.

It goes without saying that the bandgap monitoring circuit 38 does nothave to be restricted to the bandgap principle and was mentioned hereonly by way of example, and may also be embodied differently, forexample by means of zener diodes.

Although the present invention has been described above on the basis ofpreferred exemplary embodiments, it shall not be restricted thereto, butrather can be modified in diverse ways.

Thus, the discharging circuit need not necessarily be formed by means ofan NMOS transistor, but rather could also be realized by arbitrary otherdischarging means, for example with application of a hysteresisdischarge.

In the same way, the monitoring control circuit need not necessarilyrealize an overvoltage or undervoltage detection on the basis of theoutput signal of the error detection circuit. In addition or as analternative, it would also be possible for the error detection circuitto determine this function directly on the basis of the outputpotential.

The error detection circuit also need not necessarily be restricted tothe use of a simple amplifier, although this represents a realization ofthis function which is highly elegant and simple in terms of circuitry.It should additionally be mentioned that, at the input of the errordetection circuit, the output signal can, of course, be divided down bymeans of correspondingly designed voltage dividers.

As level converter, in addition to a capacitor it is also possible toimplement other circuitry means which are suitable for shifting a firstvoltage level of the regulating potential into a different voltage levelwith respect thereto, although the use of a simple capacitor representsa highly elegant option particularly in the case of an integratedvoltage regulator. In the same, it may also be provided that, inaddition or as an alternative, a level converter is provided between theoutput terminal and an input of the area detection circuit.

Instead of no or two hysteresis ranges, it is also possible, of course,to provide only one upper or one lower hysteresis range.

1. A circuit arrangement for voltage regulation, comprising: an output,at which a voltage-regulated output potential can be tapped off; acontrollable output transistor connected to said output on a load side;said output transistor comprising a control terminal; an error detectioncircuit providing a regulating signal if a deviation between said outputpotential or a potential derived from said output potential and adesired value occurs; by means of said regulating signal said controlterminal can be charged or discharged dependent on said deviation, amonitoring control circuit monitoring said regulating signal andperforming, if said regulating signal lies outside a predeterminedrange, an additional charging or discharging of said control terminaluntil said regulating signal lies within said predetermined range. 2.The circuit arrangement of claim 1, wherein said output transistor is ann-channel MOSFET or an n-channel power MOSFET.
 3. The circuitarrangement of claim 1, wherein said output transistor is formed insource follower connection comprising a drain terminal and a sourceterminal; said drain terminal being connected to a first supplyterminal, at which said first supply potential is present, and saidsource terminal being connected to said output.
 4. The circuit of claim1, wherein said error detection circuit comprises an amplifier comparingsaid output potential or said potential derived from said outputpotential with said desired value and providing, depending on saidcomparing, on an output of said amplifier an amplified regulating signalfor driving said control terminal.
 5. The circuit of claim 4, whereinsaid amplifier is an inverting amplifier.
 6. The circuit arrangement ofclaim 1, comprising a level converter shifting a level of saidregulating signal into a control potential.
 7. The circuit arrangementof claim 6, wherein said level converter is formed as a capacitiveelement or as a capacitor.
 8. The circuit arrangement of claim 1,comprising at least one of a controllable charging designed to chargesaid control terminal with a charging current or a discharging circuitdesigned to discharge said control terminal with a discharging current.9. The circuit arrangement of claim 8, wherein said controllablecharging circuit comprises a charge pump or a charge pump equipped withpull-up transistors for providing said charging current.
 10. The circuitarrangement of claim 8, wherein said controllable discharging circuitcomprises a discharging current source or a controllable MOSFET V forproviding said discharging current.
 11. The circuit arrangement of claim8, wherein said controllable charging circuit or said controllabledischarging circuit is coupled to said monitoring control circuit; saidmonitoring control circuit V providing at least one control signal, bymeans of which said charging or said discharging circuit can beactivated or deactivated.
 12. The circuit arrangement of claim 1,wherein said error detection circuit comprises a bandgap monitoringcircuit arranged, on a supply side, between said output and a secondsupply terminal, which monitors a bandgap voltage dependent on saidoutput voltage and which generates said regulating signal on the outputside if no bandgap voltage is present.
 13. The circuit arrangement ofclaim 1, comprising a voltage divider between said output and an inputof said error detection circuit; said voltage divider dividing down saidoutput potential in a manner corresponding to a division ratio of saidvoltage divider.